Digital Verification

SoC (System-On-Chip) design adds up to a higher level of complexity making Digital Verification mandatory. As many different complex sub-system IPs (microcontroller, memory, peripherals, buses, data converters) connected together need to be tested and verified conformance regarding protocols, standards and the overall product specification. This can include cross-check simulations using simpler directed testbenches or more complex verification methodologies and environments.

The solutions we have worked on are writing cross-check verification testbenches in plain SystemVerilog, UVM or pyUVM.