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AMS verification is fundamental when designing mixed-signal ICs. RFIDO DESIGN team develop Analog/RF behavioral models (Verilog-A, Verilog-AMS and SystemVerilog) and AMS verification strategies for checking the AMS interface, interconnections, voltage levels speeding up top level simulations and increasing design confidence.
We have developed a library of high level Verilog-A/Verilog-AMS models for system level validation including monitors to automate specialized accurate measurements.
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